Many types of random access memory (RAM) circuits use transistor driven data cells to latch bits of data for memory storage and are used in a large variety of consumer electronics, such as computers and cellular telephones. Data cells in a RAM circuit are typically arranged in an array, such that the RAM includes individually addressable rows and columns to which data can be written and from which data can be read. The individually addressable rows and columns are controlled by peripheral circuitry that receives decoded signals corresponding to memory locations, which could be generated from a processor, such that the peripheral circuitry determines which of the data cells in the array are written to or read from at any given time.
The market for consumer electronics, however, is constantly improving. There is an increasing demand to add more functionality and improve performance of current products while consuming less power for the purpose of conserving battery-life, such as in wireless communication applications. A given memory array of a RAM may require a higher operating voltage for read/write operations, but such a higher voltage potential may not be needed by associated peripheral circuitry to address the memory array for the read/write operations during less performance intensive memory operations. Therefore, one attempt to achieve lower power consumption is to reduce the operating voltage of the peripheral circuitry relative to the read/write voltage of memory cells in the memory array for less performance intensive memory operations. A level-shifter circuit is commonly used for this dual voltage-supply memory array system, such that the voltage potential of the peripheral circuitry can be reduced relative to the read/write voltage of the memory cells in the memory array to achieve lower power consumption while maintaining operational integrity of the memory circuit.
FIG. 1 illustrates a prior art example of a memory peripheral circuit 10. The memory peripheral circuit 10 includes a pre-decoder circuit 12. The pre-decoder circuit 12 receives inputs (not shown) from, for example, a processor to generate a three-bit decoding system for activating a given word-line, for example, to address a memory row of a memory array. In the example of FIG. 1, the pre-decoder 12 generates a pre-decode signal PRE_A, a pre-decode signal PRE_B, and a pre-decode signal PRE_C, each at a voltage VDDL when logic-high. The three pre-decode signals PRE_A, PRE_B, and PRE_C are each input to a decoder circuit 14. The decoder circuit 14 includes a NAND-gate 16, a level-shifter 18, and an inverter 20. The NAND-gate 16 receives the three pre-decode signals PRE_A, PRE_B, and PRE_C and generates a decode signal at a node 22 that is input to the level-shifter 18. As described above, each of the three pre-decode signals PRE_A, PRE_B, and PRE_C are at a voltage VDDL when logic-high, which could be an operating voltage that is less than an operating voltage required for read/write operations to an associated memory array (not shown), such that power consumption can be reduced. Accordingly, the level-shifter 18 can increase the voltage potential of the decode signal and output a level-shifted decode signal at a node 24, the level-shifted decode signal having a logic-high voltage VDDH that is greater than the voltage VDDL. The level-shifted decode signal is then inverted by the inverter 20 to generate a decode signal WL at a node 26. The decode signal WL, having a voltage VDDH when logic-high, activates a word-line to address a memory row of the associated memory array for read/write operations.
As described above, the example of FIG. 1 results in reduced power consumption as the peripheral circuitry operates at a lower voltage potential than the voltage necessary for read/write operations. However, the addition of logic gates and transistor switches to a given circuit introduces additional latency in activating a word-line to perform the read/write operations of a memory row. Accordingly, the reduction of power consumption of the memory peripheral circuit 10 of FIG. 1 sacrifices performance, as the addition of the level-shifter 18 increases latency in the decoding of the three pre-decode signals PRE_A, PRE_B, and PRE_C to assert the decode signal WL.
To demonstrate the latency stages of the memory peripheral circuit 10 of FIG. 1, it is to be understood that a latency stage can be latency resulting from the activation of a transistor by biasing a gate terminal. For example, the NAND-gate 16 can result in a single latency stage at the node 22 because a typical NAND-gate generates an output from the approximately simultaneous activation of one or more transistors. The level-shifter 18 can result in two latency stages at the node 24, as may be characteristic of the sequential activation of two transistors of a typical level-shifter. Additionally, the inverter 20 can result in a latency stage at the node 26 because a typical inverter generates an output from the activation of one of two transistors. Therefore, the assertion of the decode signal WL at the node 26 may have undergone four total stages of latency through the decoder circuit 14. Accordingly, the reduction of power consumption in the memory peripheral circuit 10 may result in a decrease in operating performance of the RAM associated with a given memory system.